ADSP-21368 SHARC Processor Hardware Reference 6-25
Serial Peripheral Interface Ports
Without disabling the SPI:
1. Clear the
RXSPIx/TXSPIx registers and the buffer status without dis-
abling the SPI by ORing 0xc0000 with the present value in the
SPICTLx registers. Use the RXFLSH (bit 19) and TXFLSH (bit 18) bits
in the SPICTLx registers to clear the RXSPIx/TXSPIx registers and
the buffer status.
2. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMACx
registers. This ensures that any data from a previous DMA opera-
tion is cleared because the SPICLK signal runs for five more word
transfers even after the DMA count is zero in receive DMA.
3. Clear all errors by writing to the W1C-type bits in the SPISTATx
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
4. Reconfigure the SPICTLx registers to remove the clear condition on
the TXSPIx/RXSPIx registers.
5. Configure DMA by writing to the DMA parameter registers
(described in Table 2-6 on page 2-29) and the SPIDMACx registers
using the SPIDEN bit (bit 0).
DMA Error Interrupts
The
SPIUNF and SPIOVF bits of the SPIDMACx registers indicate transmission
errors during a DMA operation in slave mode. When one of the bits is set,
an SPI interrupt occurs. The following sequence details the steps to
respond to this interrupt.
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