S/PDIF Transmitter
9-10 ADSP-21368 SHARC Processor Hardware Reference
SRU1 Signals for the S/PDIF Transmitter
To use the transmitter, route the five required inputs using SRU1 as
described below. Also, use SRU1 to connect the two outputs, bi-phase
encoded output, and block start to the desired DAI (digital audio inter-
face) pin.
DIT_CLK_I is the serial clock. It controls the rate at which serial data
enters the S/PDIF module. This is typically 64 time slots
1
. The SCLK input
to the S/PDIF transmitter is controlled by the 5-bit clock routing (SRU1
group A) register field SRU_CLK2[14:10] (DIT_CLK_I). This clock input can
come from the SPORTS, the PCG, external pins, or from the S/PDIF
receiver. By default it is connected to LOGIC_LEVEL_LOW. For more infor-
mation, see “Group A Connections—Clock Signals” on page 4-19.
DIT_DAT_I provides serial data. The format of the serial data can be I
2
S
and right/left-justified. The SDATA input to the S/PDIF transmitter is con-
trolled by the 6-bit serial data routing (SRU1 group B) register field
SRU_DAT4[5:0] (DIT_DAT_I). The data input can come from the SPORTs,
the SRC, external pins, or from the S/PDIF receiver. By default, SDATA is
connected to external pin 0. For more information, see “Group B Connec-
tions—Data Signals” on page 4-25.
DIT_FS_I is the frame sync input to the S/PDIF transmitter. It is con-
trolled by the 5-bit LRCLK routing (SRU1 group C) register field
SRU_FS2[14:10]. The frame sync input can come from the SPORTs, the
PCGs, external pins, or from the S/PDIF receiver. By default the frame
sync is connected to LOGIC_LEVEL_LOW. For more information, see “Group
C Connections—Frame Sync Signals” on page 4-31.
1
Timing for the S/PDIF format consists of time slots, unit intervals, subframes and frames. For a com-
plete explanation of S/PDIF timing, see one of the digital audio interface standards listed at the begin-
ning of this chapter.
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