PWM Implementation
8-16 ADSP-21368 SHARC Processor Hardware Reference
PWM Pins and Signals
The entire PWM module has four groups of four PWM outputs, for a
total of 16 PWM outputs. The modules are controlled by the PWM_AH and
PWM_BH pins which produce high side drive signals and the PWM_AL and
PWM_BL pins which produce low side drive signals. These are shown in
Figure 8-1 on page 8-2.
Each PWM group is able to generate complementary signals on two out-
puts in paired mode or each group can provide independent outputs in
non-paired mode.
The switching frequency and dead time of the generated PWM patterns
are programmable using the PWMPERIODx and PWMDTx registers. In addition,
two duty cycle control registers (PWMAx and PWMBx) directly control the
duty cycles of the two pairs of PWM signals. In non-paired mode the low
side signals can have different duty cycles programmed through another
pair of registers (PWMALx and PWMBLx). It should be further noted that the
choice of center or edge-aligned mode applies to a single group of four
PWM waveforms. Each of the four PWM output signals can be enabled or
disabled by separate output enable bits in the PWMSEG0–3 register (see
“PWM Output Disable Registers (PWMSEGx)” on page A-82). Addition-
ally, in center-aligned paired mode, an emergency dead time insertion
circuit enforces a dead time defined by the PWMDT0–3 registers between the
high and low side drive signals of each PWM channel. This ensures that
the correct dead time occurs at the power inverter. In many applications,
there is a need to provide an isolation barrier in the gate-drive circuits that
turn on the power devices of the inverter.
Crossover
The
PWMSEG3–0 registers contain four bits, one for each PWM output (see
Table A-28 on page A-82). If crossover mode is enabled for any pair of
PWM signals, the high side PWM signal from the timing unit (for exam-
ple AH) is diverted to the associated low side output of the output control
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