Two Wire Interface Registers
A-154 ADSP-21368 SHARC Processor Hardware Reference
8-Bit Receive FIFO Register (RXTWI8)
The TWI FIFO receive data 8-bit register (RXTWI8, shown in Figure A-71)
holds an 8-bit data value read from the FIFO buffer. Receive data is read
from the corresponding receive buffer in a first-in first-out order.
Although peripheral bus reads are 32 bits, a read access to RXTWI8 can only
access one receive data byte from the FIFO buffer. With each access, the
receive status (TWIRXS) field in the TWIFIFOSTAT register is updated. If an
access is performed while the FIFO buffer is empty, the core waits until
there is at least one byte in the receive FIFO buffer and then completes the
read access. All bits in this register are read-only.
16-Bit Receive FIFO Register (RXTWI16)
The TWI FIFO receive data-double byte register (RXTWI16, shown in
Figure A-72) holds a 16-bit data value read from the FIFO buffer. To
reduce interrupt output rates and peripheral bus access times, a dou-
ble-byte receive data access can be performed. Two data bytes can be read,
effectively emptying the receive FIFO buffer with a single access. The data
is read in little-endian byte order, as shown in Figure A-72, where byte 0
is the first byte received and byte 1 is the second byte received. With each
access, the receive status (
TWIRXS) field in the TWIFIFOSTAT register is
updated to indicate it is empty. If an access is performed while the FIFO
buffer is not full, the core waits until the receive FIFO buffer is full and
then completes the read access. All bits in this register are read-only.
Figure A-71. 8-Bit Receive FIFO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
RCVDATA8[7:0]
(Receive FIFO 8-Bit
Data)
RXTWI8 (0x4488)
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