ADSP-21368 SHARC Processor Hardware Reference 3-79
External Port
Shared Memory Interface
The ADSP-21368 processor supports connections to a common shared
external memory of other ADSP-21368 processors. These connections
create shared external bus processor systems. This support includes:
• Support for asynchronous memory and SDRAM
• Distributed, on-chip arbitration for the shared external bus
• Fixed and rotating priority bus arbitration
• Bus time-out logic
• Bus lock
Figure 3-14 illustrates a basic shared memory system. In a system with
several processors sharing the external bus, any of the processors can
become the bus master. The bus master has control of the bus, which con-
sists of the DATA31-0 and ADDR23-0 pins and associated control lines.
L
In a shared memory system, programs should not reset the current
bus master as this leads to system synchronization problems.
Shared Memory Bus Arbitration
Multiple processors can share the external bus with no additional arbitra-
tion logic as shown in Figure 3-14. Arbitration logic is included on chip to
allow the connection of up to four ADSP-21368 processors.
The processor accomplishes bus arbitration through the
BR1-4 signals
which arbitrate between multiple processors. The priority scheme for bus
arbitration is determined by the
RPBA pin setting. Table 3-30 defines the
processor pins used in multiprocessing systems.
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