ADSP-21368 SHARC Processor Hardware Reference 13-1
13 PRECISION CLOCK
GENERATORS
The precision clock generators (PCG) consist of four units, each of which
generates a pair of signals (clock and frame sync) derived from a clock
input signal. The units, A B, C, and D, are identical in functionality and
operate independently of each other. The two signals generated by each
unit are normally used as a serial bit clock/frame sync pair.
Note the definitions of various clock periods that are a function of CLKIN
and the appropriate ratio control (Table 13-1).
The unit that generates the bit clock is relatively simple, since digital clock
signals are usually regular and symmetrical. The unit that generates the
frame sync output, however, is designed to be extremely flexible and capa-
ble of generating a wide variety of framing signals needed by many types
of peripherals that can be connected to the signal routing unit (SRU1).
For more information, see “Signal Routing Units” on page 4-8.
Table 13-1. Clock Periods
Timing Requirements Description
t
CK
CLKIN clock period
t
CCLK
Processor core clock period
t
PCLK
Peripheral clock period = 2 × t
CCLK
To Next Page
Loading...
Need help?
General
