ADSP-21368 SHARC Processor Hardware Reference 4-19
Digital Audio/Digital Peripheral Interfaces
Group A Connections—Clock Signals
Group A is used to route the following signals to clock inputs and are
selected from the list of group A sources.
• SPORTs clock inputs (when the SPORTs are in clock slave mode)
• Clock inputs to the eight IDP (input data port) channels
• Four precision clock generator (PCG) external sources
• SRC clock inputs
• SPDIF transmitter clock inputs
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When channel 0 of the IDP is configured for PDAP input, the
clock source set here is used as the parallel word latch instead of the
serial bit clock.
Set all clock inputs that are not used to logic low. Any IDP channels that
receive clock signals as set here send data to the FIFO. When a SPORT is
used as a clock master, setting the unused SPORT clock input to logic low
improves signal integrity. The registers are shown in Figure 4-12 through
Figure 4-17. The input and output signals for group A are summarized in
Table 4-4 on page 4-23.
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The following notes apply to the group A connections
1. The
SRU_CLK4–0 registers are 30-bit registers. On reads, bits
30 and 31 always return zero.
2. SPORTs 6 and 7 receive their clocks from other sources but
cannot send their own clocks to other SPORTs or other
peripherals internally through SRU. If needed, they have to
be connected externally through pins.
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