Making Connections in the SRUs
4-20 ADSP-21368 SHARC Processor Hardware Reference
3. Setting
SRU_CLK4[4:0] = 0x1C connects PCG_EXTA_I to logic
low, not PCG_CLKA_O.
Setting SRU_CLK4[9:5] = 0x1D connects PCG_EXTB_I to
logic low, not PCG_CLKB_O.
Figure 4-12. SRU_CLK0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0001001010010011
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0001100001100001
SPORT5_CLK_I
Serial Port 5 Clock Input
SPORT3_CLK_I
Serial Port 3 Clock Input
SPORT4_CLK_I
Serial Port 4 Clock Input
SPORT2_CLK_I
Serial Port 2 Clock Input
SPORT1_CLK_I
Serial Port 1 Clock Input
SPORT0_CLK_I
Serial Port 0 Clock Input
SRU_CLK0 (0x2430)
SPORT3_CLK_I
Reset = 0x252630C2
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