Error Handling
9-22 ADSP-21368 SHARC Processor Hardware Reference
Bits 0–3 of channel status byte 1 are decoded by the receiver to determine
one of the following:
• 0111 = single-channel, double-frequency mode
• 1000 = single-channel, double-frequency mode – stereo left
• 1001 = single-channel, double-frequency mode – stereo right
Error Handling
The following five types of errors can occur in the receiver and are
reported on the error flag bits.
1. Lock Error. When bit 4 in the DIRSTAT register is set (=1), the PLL
is locked.
2. Bi-phase Error. When bit 7 in the DIRSTAT register is set (=1), it
indicates that a bi-phase error has occurred and the data sampled
from the bi-phase stream may not be correct.
3. Parity Error. When bit 6 in the DIRSTAT register is set (=1), it indi-
cates that the AES3/SPDIF stream was received with the correct
even parity. When the DIR_PARITYERROR bit is low (=0), it indicates
that an error has occurred and the parity is odd.
4. CRCC Error. The
CRCCERROR bit is asserted high whenever the
CRCC check of the
DIR_B0CHANL/R bits fails. The CRCC check is
only performed if the channel status bit 0 of byte 0 is high, indicat-
ing professional mode.
5. No Stream Error. The
DIR_NOSTREAM bit is asserted whenever the
AES3/SPDIF stream is disconnected.
When the DIR_NOSTREAM bit is asserted and the audio data in the stream is
linear PCM, the receiver performs a soft mute of the last valid sample
from the AES3/SPDIF stream. A soft mute consists of taking the last valid
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