Clock Signal Options
5-36 ADSP-21368 SHARC Processor Hardware Reference
not allowed. Only standard DSP serial, left-justified sample pair,
and I
2
S modes support internal loopback. In loopback, each
SPORT can be configured as transmitter or receiver, and each
SPORT is capable of generating an internal frame sync and clock.
Any of the four paired SPORTs can be set up to transmit or receive,
depending on their SPTRAN bit configurations.
Clock Signal Options
Each SPORT has a clock signal (SPORTx_CLK) for transmitting and receiv-
ing data on the two associated data signals. The clock signals are
configured by the ICLK and CKRE bits of the SPCTLx control registers. A sin-
gle clock signal clocks both A and B data signals (either configured as
inputs or outputs) to receive or transmit data at the same rate.
The serial clock can be independently generated internally or input from
an external source. The ICLK bit of the SPCTLx control registers determines
the clock source.
When ICLK is set (=1), the clock signal is generated internally by the pro-
cessor and the SPORTx_CLK signals are outputs. The clock frequency is
determined by the value of the serial clock divisor (CLKDIV) in the DIVx
registers.
When
ICLK is cleared (=0), the clock signal is accepted as an input on the
SPORTx_CLK signals, and the serial clock divisors in the DIVx registers are
ignored. The externally-generated serial clock does not need to be syn-
chronous with the processor’s system clock. Refer to Table 5-10 on
page 5-70.
To Next Page
Loading...
Need help?
General
