PWM Implementation
8-12 ADSP-21368 SHARC Processor Hardware Reference
where subscript 1 refers to the value of that register during the first half
cycle and subscript 2 refers to the value during the second half cycle. The
corresponding duty cycles are:
since for the general case in double- update mode, the switching period is
given by:
Again, the values of T
AH
and T
AL
are constrained to lie between zero and
T
S
. Similar PWM signals to those illustrated in Figure 8-2 and Figure 8-3
can be produced on the BH and BL outputs by programming the PWMBx
registers in a manner identical to that described for the PWMAx registers.
Over Modulation
The PWM timing unit is capable of producing PWM signals with variable
duty cycle values at the PWM output pins. At the extreme side of the
modulation process, settings of 0% and 100% modulation are possible.
These two modes are termed full off and full on respectively. Settings that
fall between the extremes are considered normal modulation. These set-
tings are explained in further detail below.
d
AH
T
AH
T
H
----------
1
2
---
PWMCHA
1
PWMCHA
2
PWMDT
1
PWMDT
2
––+()
PWMPERIOD
1
PWMPERIOD
2
+()
---------------------------------------------------------------------------------------------------------------------------------------
+==
d
AL
T
AL
T
S
---------
1
2
---
PWMCHA
1
PWMCHA
2
PWMDT
1
PWMDT
2
+++()
PWMPERIOD
1
PWMPERIOD
2
+()
----------------------------------------------------------------------------------------------------------------------------------------
–==
T
S
PWMPERIOD
1
PWMPERIOD
2
+()t
PCLK
×=
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