ADSP-21368 SHARC Processor Hardware Reference 3-69
External Port
Read/Write (ADSP-2137x Processors)
If the optional full page burst is select in the
SDCTL register, the SDC posts
for every read and write an address on the bus. It does not burst, this
causes that every start address of the burst is interrupted with another start
address. This mode is equivalent to no burst mode.
Burst Stop (ADSP-2137x Processors)
If the optional full page burst is selected in the
SDCTL register, the SDC
posts an address on the bus for every read and write. However if a
non-SDRAM access is latched, the SDC interrupts the full page burst pro-
tocol. By executing a burst stop command, the specific page remains open.
Figure 3-13. Read Timing Diagram (ADSP-2137x, Full Page Burst)
SDCLK
COMMAND
ACT
ACT
NOP
NOP
PRERD RD NOP NOP BST
COL COL
AA
DD
ROW
A A
RO W
A
t
RAS
t
RCD
t
RP
CL
t
RC
ADDR
BA[1:0]
DATA
SDA10
SDA10