SPI General Operations
6-12 ADSP-21368 SHARC Processor Hardware Reference
Once the
SPIDS signal’s falling edge is detected, the slave starts
sending and receiving data on active SPICLK edges.
The reception or transmission continues until SPIDS is released.
The slave device continues to receive or transmit with each new
active SPICLK clock edge while the SPIDS signal is active.
In slave mode, if the transmit buffer remains empty, or the receive buffer
remains full, the devices operate according to the states of the SENDZ and
GM bits in the SPICTLx registers.
•If SENDZ = 1 and the transmit buffer is empty, the device repeatedly
transmits zeros on the MISO pin.
•If SENDZ = 0 and the transmit buffer is empty, the device repeatedly
transmits the last word it transmitted before the transmit buffer
became empty.
•If GM = 1 and the receive buffer is full, the device continues to
receive new data from the MOSI pin, overwriting the older data in
the RXSPI buffer.
•If GM = 0 and the receive buffer is full, the incoming data is dis-
carded, and the RXSPIx registers are not updated.
Multimaster Operation
A multimaster mode is implemented in the processor to allow an SPI sys-
tem to transfer mastership from one SPI device to another. In a
multidevice SPI configuration, several SPI ports are connected and any
one (but only one) can become a master at any given time.
If a processor is a slave and wishes to become the SPI master, it asserts the
SPIDS pin for the processor that is currently master and then drives the
SPICLK signal. Once the master device receives the SPIDS signal, it is
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