ADSP-21368 SHARC Processor Hardware Reference 11-5
UART Port Controller
This 32-bit write only register uses only 18-bits. The other bits are filled
with zeros during writes. In no-pack mode (default), only the lower byte is
used—all other bits are zero filled. However in pack mode, both the high
and low bytes are used (Figure 11-2). The
TX9Dx bits are the ninth bit in
9-bit transmission mode. This register is mapped to the same address as
the UARTxRBR and UARTxDLL registers. A write to the UART transmit hold-
ing register (UARTxTHR) initiates the transmit operation.
To access the UARTxTHR register, the UARTDLAB bit in the UARTxLCR register
must be cleared. When the UARTDLAB bit is cleared, writes to this address
target the UARTxTHR register, and reads from this address return the UAR-
TxRBR register.
Note that data is transmitted and received by the least significant bit
(LSB) first (bit 0) followed by the most significant bits (MSBs).
UARTxRBR Register
The receive operation uses the same data format as the transmit configura-
tion, except that the number of stop bits is always assumed to be 1. After
detection of the start bit, the received word is shifted into the receive shift
register (UARTxRSR) at a baud rate of PCLK/(16 x Divisor). After the appro-
priate number of bits (including stop bit) is received, the data and any
status are updated and the UARTxRSR register is transferred to the UART
receive buffer register (UARTxRBR), shown in Figure 11-3 and Figure A-51
on page A-122. After the transfer of the received word to the
UARTxRBR
buffer and the appropriate synchronization delay, the data ready status
flag (
UARTDR) is updated.
Figure 11-2. Transmit Holding Register (Packing Enabled)
31
0781524 23
TX9D0
9
TX9D1 ZERO-FILLED
LOWER BYTE
HIGHER BYTEZERO-FILLED
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