Making Connections in the SRUs
4-18 ADSP-21368 SHARC Processor Hardware Reference
Just as DAI group A routes clock signals, each of the other groups route a
collection of compatible signals. Group B routes serial data streams while
group C routes frame sync signals. Group D routes signals to pins so that
they may be driven off chip. Note that all of the groups have an encoding
that allows a signal to flow from a pin output to the input being specified
by the bit field. However, group D is required to route a signal to the pin
input. Group F routes signals to the pin enables, and the value of these
signals determines if a DAI pin is used as an output or an input. These
groups are described in more detail in the following sections.
DAI/SRU1 Connection Groups
The DAI/SRU1 has the default configuration shown in Table 4-3.
There are five separate groups of connections that are used in SRU1. The
following sections summarize each.
Table 4-3. DAI/SRU1 Default Configuration
Pin Number Signal Name Pin Number Signal Name
DAI_01 SPORT0_DA DAI_11 SPORT3_DA
DAI_02 SPORT0_DB DAI_12 SPORT3_DB
DAI_03 SPORT0_CLK DAI_13 SPORT3_CLK
DAI_04 SPORT0_FS DAI_14 SPORT3_FS
DAI_05 SPORT1_DA DAI_15 SPORT4_DA
DAI_06 SPORT1_DB DAI_16 SPORT4_DB
DAI_07 SPORT1_CLK DAI_17 SPORT5_DA
DAI_08 SPORT1_FS DAI_18 SPORT5_DB
DAI_09 SPORT2_DA DAI_19 SPORT5_CLK
DAI_10 SPORT2_DB DAI_20 SPORT5_FS
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