UART Control and Status Registers
A-122 ADSP-21368 SHARC Processor Hardware Reference
Receive Buffer Registers (UARTxRBR)
These read-only registers (shown in Figure A-51) are mapped to the same
address as the write-only UARTxTHR and DLL registers. To access UARTxRBR,
the UARTDLAB bit in the UARTxLCR register must be cleared. When the
UARTDLAB bit is cleared, writes to this address target the UARTxTHR registers,
while reads from this address return the UARTxRBR registers.
There are also shadow registers, UARTxRBRSH, with the following addresses:
UART0RBRSH (0x3C08) and UART1RBRSH (0x4008). These registers allow
programs to read the contents of the corresponding main register without
affecting the status of the UART.
Figure A-51. UART Receive Buffer Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
Higher Byte
UART0RBR (0x3C00)
UART1RBR (0x4000)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Lower Byte
RX9D0
RX9D1
Zero-Filled
Zero-Filled
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