ADSP-21368 SHARC Processor Hardware Reference 14-19
System Design
/* Core clock = (24.576 MHz * 27) /2 = 331.776 MHz */
pmctlsetting= SDCKR2|PLLM27|PLLD2|DIVEN;
*pPMCTL= pmctlsetting;
pmctlsetting|= PLLBP;
*pPMCTL= pmctlsetting;
pmctlsetting ^= DIVEN;
/* Wait for around 4096 cycles for the pll to lock. */
for (i=0; i<4096; i++)
asm("nop;");
*pPMCTL ^= PLLBP; /* Clear Bypass Mode */
*pPMCTL |= (CLKOUTEN); /* and start clkout */
Phase-Locked Loop Startup
The RESET signal can be held low long enough to guarantee a stable CLKIN
source and stable VDDINT/VDDEXT power supplies before the PLL is reset.
The PLL needs time to lock to the CLKIN frequency before the core can
execute or begin the boot process. A delayed core reset (RESETOUT) has
been added through the delay circuit to provide this time. There is a
12-bit counter that counts up to 4096 CLKIN cycles after RESET is transi-
tioned from low to high. This is normally 1.3 μs for the minimum CLKIN
frequency. The delay circuit is activated at the same time the PLL is taken
out of reset.
The advantage of the delayed core reset is that the PLL can be reset any
number of times without having to power down the system. If there is a
brownout situation, the watchdog circuit only has to control the
RESET.
L
For more information on device power up, see the processor spe-
cific data sheet.
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