Serial Port Registers
A-40 ADSP-21368 SHARC Processor Hardware Reference
SPORT Multichannel Control Registers (SPMCTLx)
Unlike previous SHARC designs, the serial ports in the ADSP-21367/8/9
and ADSP-2137x processors work individually, not in pairs. Therefore,
each SPORT has its own multichannel control register. These registers are
shown in Figure A-19 and described in Table A-9. The reset value for
these registers is undefined and their addresses are:
29 DERR_A
(TUVF_A or
ROVF_A)
Channel A Error Status (sticky, read-only). Indicates if the serial
transmit operation has underflowed or a receive operation has over-
flowed in the channel A data buffer.
31–30 DXS_A Channel A Data Buffer Status (read-only). Indicates the status of the
11 = Full
00 = Empty
10 = Partially full
SPMCTL0 – 0xC04
SPMCTL1 – 0xC17
SPMCTL2 – 0x404
SPMCTL3 – 0x417
SPMCTL4 – 0x804
SPMCTL5 – 0x817
SPMCTL6 – 0x4804
SPMCTL7 – 0x4817
Table A-8. SPCTLx Register Bit Descriptions (Cont’d)
Bit Name Description
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