Analog Devices SHARC ADSP-21368 - Page 689

ADSP-21368 SHARC Processor Hardware Reference A-41
Register Reference
Figure A-19. SPMCTLx Registers – Multichannel Mode
31 30 29 28 27 26 24 23 22 21 20 19 18 17 16
0000000000000000
DMACHSxB
SPORTx Channel B Status
DMA Chaining Status
x = 0,2,4,6
CHNL
Current Channel Status
(read-only)
DMASxA
SPORTx Channel A DMA
status x = 0,2,4,6
MCEB
Multichannel Enable
B Channels
0=Disable
1=Enable
DMACHSxA
SPORTx Channel A Status
DMA Chaining Status x = 0,2,4,6
DMACHSyB
SPORTx Channel B Status
DMA Chaining Status y = 1,3,5,7
DMACHSyA
SPORTx Channel A Status
DMA Chaining Status y = 1,3,5,7
DMASyB
SPORTx Channel B DMA Status
y = 1,3,5,7
DMASyA
SPORTx Channel A DMA
Status y = 1,3,5,7
DMASxB
SPORTx Channel B DMA
status x = 0,2,4,6
15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
0000000000000000
Reserved
SPL
MCEA
Multichannel Enable
A Channels
1=Enable
0=Disable
MFDx
Multichannel Frame Delay
SPORT Loopback
SPORT0 A to SPORT1 A only
SPORT0 B to SPORT1 B only
NCH
Number of Channels – 1
25
9
SPMCTL0 (0xC04) SPMCTL1 (0xC17)
SPMCTL2 (0x404) SPMCTL3 (0x417)
SPMCTL4 (0x804) SPMCTL5 (0x817)
SPMCTL6 (0x4804) SPMCTL7 (0x4817)