SPORT Operation Modes
5-18 ADSP-21368 SHARC Processor Hardware Reference
To transmit or receive words continuously in left-justified sample pair
mode, load the
DIV register with the FSDIV value the same as SLEN. For
example, for 8-bit data words where SLEN = 7, set FSDIV = 7.
Enabling SPORT Master Mode (MSTR)
The SPORTs transmit and receive channels can be configured for master
or slave mode. In master mode (MSTR = 1), the processor generates the
word select and serial clock signals for the transmitter or receiver. In slave
mode (MSTR = 0), an external source generates the word select and serial
clock signals for the transmitter or receiver. For more information, see
“Setting the Internal Serial Clock and Frame Sync Rates” on page 5-17.
Selecting Transmit and Receive Channel Order (FRFS)
Using the FRFS bit, it is possible to select which frame sync edge (rising or
falling) on which the serial ports transmit or receive the first sample. See
Table 5-1 on page 5-11 for more details.
Selecting Frame Sync Options (DIFS)
When using both SPORT channels (SPORTx_DA and SPORTx_DB) as trans-
mitters and MSTR = 1, SPTRAN = 1, and DIFS = 0, the processor generates a
frame sync signal only when both transmit buffers contain data.This is
because both transmitters share the same
FSDIV and SPORTx_FS. For con-
tinuous transmission, both transmit buffers must contain new data.
When using both SPORT channels as transmitters and MSTR = 1,
SPTRAN = 1 and DIFS = 1, the processor generates a frame sync signal at the
frequency set by FSDIVx, whether or not the transmit buffers contain new
data. The DMA controller or the application is responsible for filling the
transmit buffers with data.
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