ADSP-21368 SHARC Processor Hardware Reference 8-17
Pulse Width Modulation
unit so that the signal ultimately appears at the
AL pin. The corresponding
low side output of the timing unit is also diverted to the complementary
high side output of the output control unit so that the signal appears at
the AH pin. Following a reset, the three crossover bits are cleared so that
the crossover mode is disabled on all three pairs of PWM signals. Even
though crossover is considered an output control feature, dead time inser-
tion occurs after crossover transitions as necessary to eliminate shoot
through safety issues.
PWM Accuracy
The PWM has 16-bit resolution but accuracy is dependent on the PWM
period. In single-update mode, the same values of PWMA and PWMB are used
to define the on-times in both half cycles of the PWM period. As a result
the effective accuracy of the PWM generation process is 2tPCLK (or 20 ns
for a 100 MHz clock). Incrementing one of the duty cycle registers by one
changes the resultant on-time of the associated PWM signals by tPCLK in
each half period (or 2tPCLK for the full period). In double-update mode,
improved accuracy is possible since different values of the duty cycles reg-
isters are used to define the on-times in both the first and second halves of
the PWM period. As a result, it is possible to adjust the on-time over the
whole period in increments of t
PCLK
. This corresponds to an effective
PWM accuracy of t
PCLK
in double-update mode (or 10 ns for a 100 MHz
clock). The achievable PWM switching frequency at a given PWM accu-
racy is tabulated in Table 8-1.
Table 8-1. PWM Accuracy in Single and Double-Update Modes
Resolution (bits) Single-Update Mode
PWM Frequency (kHz)
Double-Update Mode
PWM Frequency (kHz)
8 195.3 390.6
997.7 195.3
10 48.8 97.7
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