UART Control and Status Registers
A-124 ADSP-21368 SHARC Processor Hardware Reference
Interrupt Identification Registers (UARTxIIR)
For legacy reasons, the UART interrupt identification registers (UARTxIIR,
shown in Figure A-53) still reflect the UART interrupt status. Legacy
operation may require bundling all UART interrupt sources to a single
interrupt channel and servicing them all by the same software routine.
This can be established by globally assigning all UART interrupts to the
same interrupt priority. For more information, see “Peripheral Interrupt
Priority Control Registers” on page A-164.
There are also shadow registers, UARTxIIRSH, with the following addresses:
UART0IIRSH (0x3C09) and UART1IIRSH (0x4009). These registers allow
programs to read the contents of the corresponding main register without
affecting the status of the UART.
Figure A-53. UART Interrupt Identification Register
UARTISTAT
In the order of interrupt priority, highest first.
011=Receive line status. Read UART_LSR to clear interrupt request.
100=Address detect. Read RBR to clear interrupt request.
010=Receive data ready. Read UART RBR to clear interrupt request.
001=UART_THR empty. Write UART_THR or read UART_IIR to clear
interrupt request, when priority = 4.
000=UART THR & TSR empty (TEMT = transmit complete). Write
UART_THR or read UART_IIR to clear interrupt request, when priority = 5.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000000000000000
UART0IIR (0x3C02)
UART1IIR (0x4002)
Pending Interrupt
0=Interrupt pending
1=No interrupt pending
UARTNOINT
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