Analog Devices SHARC ADSP-21368 User Manual

ADSP-21368 SHARC Processor Hardware Reference 7-31
Input Data Port
Input Data Port Programming Example
Listing 7-1 shows a data transfer using an interrupt service routine (ISR).
The transfer takes place through the digital applications interface (DAI).
This code implements the algorithm outlined in “FIFO to Memory Data
Transfer” on page 7-16.
Listing 7-1. Interrupt-Driven Data Transfer
/* Using Interrupt-Driven Transfers from the IDP FIFO */
#define IDP_ENABLE (8) /* IDP_ENABLE = IDP_CTL0[7] */
#define IDP_CTL0 (0x24B0) /* Memory-mapped register */
#define IDP_FIFO_GTN_INT (8) /* Bit 8 in interrupt regs */
#define IDP_FIFO (0x24D0) /* IDP FIFO packing mode */
#define DAI_IRPTL_FE (0x2480) /* Falling edge int latch */
#define DAI_IRPTL_RE (0x2481) /* Rising edge int latch */
#define DAI_IRPTL_PRI (0x2484) /* Interrupt priority */
.section/dm seg_dmda;
.var OutBuffer[6];
.section/pm seg_pmco;
initIDP:
r0 = dm(IDP_CTL0); /* Reset the IDP */
r0 = BSET r0 BY IDP_ENABLE;
dm(IDP_CTL0) = r0;
r0 = BCLR r0 BY IDP_ENABLE;
r0 = BCLR r0 BY 10; /* Set IDP serial input channel 0 */
r0 = BCLR r0 BY 9; /* to receive in I2S format */
r0 = BCLR r0 BY 8;

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP