ADSP-21368 SHARC Processor Hardware Reference 5-25
Serial Ports
Interrupt-Driven Data Transfer Mode
Both the A and B channels share a common interrupt vector in the inter-
rupt-driven data transfer mode, regardless of whether they are configured
as a transmitter or receiver.
The SPORT generates an interrupt when the transmit buffer has a
vacancy or the receive buffer has data. To determine the source of an
interrupt, applications must check the transmit or receive data buffer sta-
tus bits. For more information, see “Single Word Transfers” on page 5-81.
DMA-Driven Data Transfer Mode
Each transmitter and receiver has its own DMA registers. For details, see
“Selecting Transmit and Receive Channel Order (FRFS)” on page 5-18
and “Moving Data Between SPORTs and Internal Memory” on
page 5-73. The same DMA channel drives the left and right I
2
S channels
for the transmitter or the receiver. The software application must stop
multiplexing the left and right channel data received by the receive buffer,
because the left and right data is interleaved in the DMA buffers.
Channel A and B on each SPORT share a common interrupt vector. The
DMA controller generates an interrupt at the end of DMA transfer only.
Figure 5-4 shows the relationship between frame sync (word select), serial
clock, and I
2
S data. Timing for word select is the same as for frame sync.
L
The SPL bit applies to DSP standard serial and I
2
S modes only.
Multichannel Operation
The processor’s SPORTs offer a multichannel mode of operation, which
allows the SPORT to communicate in a time division multiplexed (TDM)
serial system. In multichannel communications, each data word of the
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