SPI General Operations
6-10 ADSP-21368 SHARC Processor Hardware Reference
Master Mode Operation
When the SPI is configured as a master, configure the SPI port and start
transfers using the following steps:
1. Before enabling the SPI port, programs should specify which of the
slave-select signals to use, setting one or more of the required SPI
flag select bits (DSxEN) in the SPIFLGx registers.
2. Write to the SPICTLx and SPIBAUDx registers, enabling the device as
a master and configuring the SPI system by specifying the appro-
priate word length, transfer format, baud rate, and other necessary
information.
When CPHASE is set to 0, the slave-select signals are automatically
controlled by the SPI port. When CPHASE = 1, the slave selects are
controlled by the core and the user software has to control the pins
through the SPIFLGx bits. If CPHASE = 1 (user-controlled,
slave-select signals), activate the desired slaves by clearing one or
more of the SPI flag bits (SPIFLGx) in the SPIFLGx registers.
3. Initiate the SPI transfer. The trigger mechanism for starting the
transfer is dependant upon the TIMOD bits in the SPICTLx registers.
See “Master Transfer Preparation” on page 6-18 for details.
The SPI generates the programmed clock pulses on
SPICLK. The
data is shifted out of
MOSI and shifted in from MISO simultaneously.
Before starting to shift, the TXSR register is loaded with the contents
of the
TXSPIx registers. At the end of the transfer, the contents of
the
RXSR register are loaded into the RXSPIx registers.
With each new transfer initiate command, the SPI continues to
send and receive words, according to the SPI transfer mode (
TIMOD
bit in the
SPICTLx registers). See “Master Transfer Preparation” on
page 6-18 for more details.
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