ADSP-21368 SHARC Processor Hardware Reference 12-9
Two Wire Interface Controller
bus access times, a double byte transfer data access can be performed. Two
data bytes can be written, effectively filling the transmit FIFO buffer with
a single access.
The data is written in little-endian byte order as shown in Figure 12-2,
where byte 0 is the first byte to be transferred and byte 1 is the second byte
to be transferred. With each access, the transmit status (
TWITXS) field in
the TWIFIFOSTAT register is updated. If an access is performed while the
FIFO buffer is not empty, the core waits until the FIFO buffer is com-
pletely empty and then completes the write access. All bits in this register
are write-only. This register always reads as 0x00000000. For more infor-
mation, see “16-Bit Transmit FIFO Register (TXTWI16)” on
page A-153.
8-Bit Receive FIFO Register
The TWI 8-bit FIFO receive register (RXTWI8) holds an 8-bit data value
read from the FIFO buffer. Receive data is read from the corresponding
receive buffer in a first-in, first-out order. Although peripheral bus reads
are 32 bits, a read access to the RXTWI8 register can only access one receive
data byte from the FIFO buffer. With each access, the receive status
(
TWIRXS) field in the TWIFIFOSTAT register is updated. If an access is per-
formed while the FIFO buffer is empty, the core waits until there is at
least one byte in the receive FIFO buffer and then completes the read
access. All bits in this register are read-only. For more information, see
“8-Bit Receive FIFO Register (RXTWI8)” on page A-154.
Figure 12-2. Little-Endian Byte Order
B1 B0
DATA IN REGISTER
0
7
816 15232431
UNUSEDUNUSED
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