SDRAM Controller
3-30 ADSP-21368 SHARC Processor Hardware Reference
External Port DMA
The AMI shares the two DMA channels of the external port with the
SDRAM controller. Either of these DMA channels can be directed to the
external asynchronous memories. For information on external port DMA,
see Chapter 2, I/O Processor.
Booting Through the AMI
The AMI supports an 8-bit user boot called AMI boot. For more informa-
tion, see “Booting Through the AMI” on page 14-39.
SDRAM Controller
The ADSP-21367/8/9 and ADSP-2137x SHARC processors support a
glueless interface with any of the standard SDRAMs of 64M bit, 128M
bit, 256M bit, and 512M bit with configurations x4, x8, x16 and x32.
The SDRAM controller (SDC) can support up to 254M words of
SDRAM in four banks. Bank 0 can accommodate up to 62M words, and
banks 1, 2, and 3 can accommodate up to 64M words each. The SDC
includes timing options to support additional buffers between the proces-
sors and SDRAM. This allows the processor to handle the capacitive loads
of large memory arrays. The following are additional features of the SDC.
• I/O width 16-bit or 32-bits, I/O supply 3.3 V
• Types of 32, 64, 128, 256, and 512M bit with I/O of x4, x8, x16
and x32
• Page sizes of 128, 256, 512, 1k, 2k words
• SDC uses no-burst mode (BL = 1) with sequential burst type
• SDC uses optional full page burst (ADSP-2137x only)
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