ADSP-21368 SHARC Processor Hardware Reference 10-19
Asynchronous Sample Rate Converter
• 10 – 44.1 kHz sample rate de-emphasis filter
• 11 – 48 kHz sample rate de-emphasis filter
After the audio data is passed from the de-emphasis filter to the SRC, the
SRC converts the audio data from the input sample rate to the output
sample rate. When the serial output port needs new data, the frame syn-
chronization signal, (UN_f
S_OUT
), is asserted from the serial output port.
Like the UN_f
S_IN
signal, the UN_f
S_OUT
signal derives its clock from
the positive edge of the PCLK signal. The UN_f
S_OUT
and UN_f
S_IN
sig-
nals are used by the SRC to perform the sample rate conversion. The
SRCRAT register indicates the sample rate ratio of UN_f
S_OUT
/UN_f
S_IN
.
Mute Control
When the SRCx_ENABLE bit is enabled (set = 1), or when the sample rate
between the input and output LRCLK changes, the SRC begins its initializa-
tion routine and the MUTE_OUT signal is asserted. When MUTE_OUT is
asserted, the MUTE_IN signal should also be asserted to avoid any unwanted
output.
When the MUTE_IN pin is asserted high, the MUTE_IN control performs a
soft mute by linearly decreasing the input data to the SRC FIFO to zero,
(–144 dB attenuation). A 12-bit counter, clocked by the LRCLK_I signal, is
used to control the mute attenuation. Therefore, the time it takes from the
assertion of the
MUTE_IN signal to –144 dB, (full mute attenuation) is 4096
LRCLK clock cycles. Likewise, the time it takes to reach 0 dB mute attenua-
tion from the deassertion of the MUTE_IN signal is 4096 LRCLK cycles.
The mute feature of the SRC can be controlled automatically in hardware
using the
MUTE_IN signal by connecting it to the MUTE_OUT signal. By
default, the two signals for each SRC are connected. Automatic muting
can be disabled using the SRCx_MUTE_DIS bits in the SRCMUTE register.
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