S/PDIF Receiver
9-18 ADSP-21368 SHARC Processor Hardware Reference
SRU1 Receiver Signals
The bi-phase encoded data and the external PLL clock inputs to the
receiver are routed through the signal routing unit (SRU1). The extracted
clock, frame sync, and data are also routed through SRU1.
The SRU1 inputs to the S/PDIF receiver are configured through the fol-
lowing signals.
• SPDIF_PLLCLK_I is the external 512 x FS (frame sync) PLL
clock input. This signal is controlled by the 5-bit clock routing reg-
ister field SRU_CLK4[14:10] (Figure 4-16 on page 4-22). This clock
input can come from the external pins connected to the external
PLL.
• DIR_I is the bi-phase encoded data input. This signal is controlled
by the 5-bit frame sync routing register field SRU_FS3[29:25]
(Figure 4-16 on page 4-22). This data may be received from exter-
nal pins or from the S/PDIF receiver.
The SRU1 outputs from the S/PDIF receiver are configured through the
following signals.
• DIR_DAT_O is the extracted audio data output. This signal can
be routed to any of the external pins or to one of the serial receivers
(SPORT, input data port) through SRU1.
• DIR_CLK_O is the extracted receiver sample clock output. This
signal can be routed to any of the external pins or to one of the
serial receivers (SPORT, input data port) through SRU1.
• DIR_FS_O is the extracted receiver frame sync out. This signal can
be routed to any of the external pins or to one of the serial receivers
(SPORT, input data port) through SRU1.
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