Parallel Data Acquisition Port (PDAP)
7-14 ADSP-21368 SHARC Processor Hardware Reference
As shown in Figure 7-15,
PDAP_DATA and PDAP_HOLD are driven by the
inactive edges of the clock (falling edge in the above figures) and these sig-
nals are sampled by the active edge of the clock (rising edge in the above
figures).
PDAP Strobe
Whenever the PDAP packing unit receives the number of subwords corre-
sponding to its select mode, it asserts the PDAP output strobe signal. This
signal can be routed through the SRU using the MISC unit to any of the
DAI pins. See “DAI/SRU1 Connection Groups” on page 4-18 for more
information.
Figure 7-15. Hold Timing for Two 16-Bit Words to 32 Bits (Mode 10)
PDAP_CLK
PDAP_DAT[19:4]
PDAP_HOLD
BA A B A B
PDAP_CLK
PDAP_DAT[19:4]
PDAP_HOLD
BA A B
B
A
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