Analog Devices SHARC ADSP-21368 User Manual

FIFO to Memory Data Transfer
7-18 ADSP-21368 SHARC Processor Hardware Reference
Starting an Interrupt-Driven Transfer
To start an interrupt-driven transfer:
1. Clear and halt FIFO by setting (= 1) and clearing (= 0) the
IDP_ENABLE bit (bit 7 in the IDP_CTL0 register).
2. Set the required values for:
• IDP_SMODEx bits in the IDP_CTL0 register to specify the frame
sync format for the serial inputs (left-justified sample pair,
right-justified sample pair, or I
2
S mode).
• IDP_Pxx_PDAPMASK bits in the IDP_PP_CTL register to specify
the input mask, if the PDAP is used.
• IDP_PORT_SELECT bits in the IDP_PP_CTL register to specify
input from the DAI pins, if the PDAP is used.
• IDP_PDAP_CLKEDGE bit (bit 29) in the IDP_PP_CTL register to
specify if data is latched on the rising or falling clock edge, if
the PDAP is used.
3. Keep the clock and frame sync inputs of all serial inputs and/or the
PDAP connected to low. Use the SRU_CLK2, SRU_CLK3, SRU_FS2,
and SRU_FS3 registers to specify these inputs. See “Group A Con-
nections—Clock Signals” on page 4-19 and “Group C
Connections—Frame Sync Signals” on page 4-31.
4. Connect all of the inputs to the IDP by writing to the
SRU_DAT4,
SRU_DAT5, SRU_FS2, SRU_FS3, SRU_CLK2, and SRU_CLK3 registers.
Connect the clock and frame sync of any unused ports to low.
5. Set the desired value for the N_SET variable (the
IDP_NSET bits,
3–0, in the
IDP_CTL0 register).

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP