ADSP-21368 SHARC Processor Hardware Reference 7-19
Input Data Port
6. Set the
IDP_FIFO_GTN_INT bit (bit 8 of the DAI_IRPTL_RE register)
to HIGH and set the corresponding bit in the DAI_IRPTL_FE register
to low to unmask the interrupt. Set bit 8 of the DAI_IRPTL_PRI reg-
ister (IDP_FIFO_GTN_INT) as needed to generate a high priority or
low priority core interrupt when the number of words in the FIFO
is greater than the value of N set.
7. Enable the PDAP by setting the IDP_PDAP_EN bit (bit 31 in the
IDP_PP_CTL register), if required.
8. Enable the IDP by setting the IDP_ENABLE bit (bit 7 in the
IDP_CTL0 register) and the IDP_ENx bits in the IDP_CTL1 register.
L
Do not set the IDP_DMA_EN bit (bit 5 of the IDP_CTL0 register) as
this enables DMA transfers.
Core Transfer Notes
The following items provide general information about interrupt-driven
transfers.
• The three LSBs of FIFO data are the encoded channel number.
These are transferred “as is” for this mode. These bits can be used
by software to decode the source of data.
• The number of data samples in the FIFO at any time is reflected in
the
IDP_FIFOSZ bit field (bits 31–28 in the DAI_STAT register),
which tracks the number of samples in FIFO.
When using the interrupt scheme, the
IDP_NSET bits (bits 3–0 of
the
IDP_CTL0 register) can be set to N, so N + 1 data can be read
from the FIFO in the interrupt service routine (ISR).
•If the
IDP_BHD bit (bit 4 in the IDP_CTL0 register) is not set,
attempts to read more data than is available in the FIFO results in a
core hang.
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