Analog Devices SHARC ADSP-21368 User Manual

Data Delays, Latencies, and Throughput
14-56 ADSP-21368 SHARC Processor Hardware Reference
DMA Stalls
• One cycle if an access to a DMA parameter register conflicts with
the DMA address generation (for example, writing to the register
while a register update is taking place) or reading while a DMA
register conflicts with DMA chaining.
• Attempting to write to (or read from) a full (or empty) DMA
buffer causes the core to hang indefinitely, unless the BHD (buffer
hang disable) bit for that peripheral is set (for example in the corre-
sponding SPCTLx register for a serial port).
IOP Buffer Stalls
Table 14-16 shows the number of stalls incurred with the I/O processor
when writing to a full buffer or reading from an empty buffer.
Table 14-16. Latencies and Throughput
Operation Minimum Data
Delay (cycles)
Maximum
Throughput
(cycles/ transfer)
Interrupts (IRQ2-0) 3 -
DMA chain initialization 7–11 -
Serial ports
1
1 ADSP-2136x SHARC processor-to-ADSP-2136x SHARC processor transfers using 32-bit
words.
35 32

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP