Data Delays, Latencies, and Throughput
14-56 ADSP-21368 SHARC Processor Hardware Reference
DMA Stalls
• One cycle if an access to a DMA parameter register conflicts with
the DMA address generation (for example, writing to the register
while a register update is taking place) or reading while a DMA
register conflicts with DMA chaining.
• Attempting to write to (or read from) a full (or empty) DMA
buffer causes the core to hang indefinitely, unless the BHD (buffer
hang disable) bit for that peripheral is set (for example in the corre-
sponding SPCTLx register for a serial port).
IOP Buffer Stalls
Table 14-16 shows the number of stalls incurred with the I/O processor
when writing to a full buffer or reading from an empty buffer.
Table 14-16. Latencies and Throughput
Operation Minimum Data
Delay (cycles)
Maximum
Throughput
(cycles/ transfer)
Interrupts (IRQ2-0) 3 -
DMA chain initialization 7–11 -
Serial ports
1
1 ADSP-2136x SHARC processor-to-ADSP-2136x SHARC processor transfers using 32-bit
words.
35 32
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