UART Control and Status Registers
11-4 ADSP-21368 SHARC Processor Hardware Reference
UARTxLSR Register
The UART line status register (UARTxLSR) contains UART status informa-
tion as shown in Figure A-49 on page A-120.
The break interrupt (UARTBI), overrun error (UARTOE), parity error
(
UARTPE), and framing error (UARTFE) bits are cleared when the UART line
status register (
UARTxLSR) is read. The data ready (UARTDR) bit is cleared
when the UART receive buffer register (UARTxRBR) is read.
L
Because of the destructive nature of reading these registers, shadow
registers are provided for reading the contents of the corresponding
main registers. The shadow registers, UARTxIIRSH, return exactly
the same contents as the main register, but without changing the
register’s status in any way. These registers are 32-bit registers
located at address 0x3C0A (for UATR0LSRSH) and 0x400A (for
UART1LSRSH).
The UARTTHRE bit (bit 6) indicates that the UART transmit channel is
ready for new data, and software can write to the UARTxTHR register. Writes
to UARTxTHR clear the UARTTHRE bit. It is set again when data is copied from
UARTxTHR to the transmit shift register (UARTxTSR). The UARTTEMT bit can
be evaluated to determine whether a recently initiated transmit operation
has been completed.
UARTxTHR Register
A write to the UART transmit holding register (UARTxTHR) initiates the
transmit operation. The data is moved to the internal transmit shift regis-
ter (UARTxTSR) where it is shifted out at a baud rate equal to
PCLK/(16 × Divisor) with start, stop, and parity bits appended as required.
All data words begin with a 1-to-0 transition start bit. The transfer of data
from the
UARTxTHR register to the transmit shift register sets the transmit
holding register empty status flag (
UARTTHRE) in the UART line status reg-
ister (UARTxLSR).
To Next Page
Loading...
Need help?
General
