ADSP-21368 SHARC Processor Hardware Reference 3-25
External Port
L
There is a 3:1 bus conflict resolution ratio at the external port
interface (three internal buses to one external bus) in addition to
the 2:1 or greater clock ratio between the processor’s internal clock
and the external SDRAM clock (SDCLK). Systems that fetch data
through the external port must tolerate at least one cycle—and pos-
sibly many additional cycles—of latency for non-SDRAM accesses.
Data alignment through the external port is identical for these interfaces.
External Memory Reads
The AMI behaves as an external port bus slave and an external read access
is performed only upon a read request from the external port control bus.
Reads from external memory are done through the AMI. When an exter-
nal address that is mapped to the AMI in the EPCTL register is accessed, the
module receives 8-, 16-, or 32-bit data and packs the data based on the
packing and control modes in the AMI control register (AMICTLx). Once
the data is received, the status bit RXS is set, indicating valid data is
present. Updates occur on a feedback RD signal and the status update
occurs on the SDCLK signal. The RXS status update is delayed by one cycle
to accommodate the delay in the feedback RD signal.
The AMI provides the interface to the external data pins as well as to the
processor core or to the internal DMA controller. When the AMI receives
data, it is passed by internal hardware to the DMA controller or to the
external port control bus, depending on which entity requested the data.
Data Packing
Data packing for memory reads is accomplished using the packing disable
(
PKDIS, bit 3) and most significant word first (bit 4 in the MSWF register)
bits in the AMICTLx register.
For packed data mode where
PKDIS = 0 and MSWF = 0, the packing order
for
BW = 8 is: first byte is bits [7–0], the second byte is bits [15–8], and so
on.
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