ADSP-21368 SHARC Processor Hardware Reference 6-15
Serial Peripheral Interface Ports
SPI transfers. For example, the
TXSPIx registers should not be used as a
scratch register for temporary data storage. Writing to the TXSPIx registers
sets the TXS bit.
When the SPI DMA engine is configured for transmitting:
1. The receive interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the receive path.
3. The RXSPIx register is used to receive data.
Similarly, when the SPI DMA engine is configured for receiving,
1. The transmit interface cannot generate an interrupt, but the status
can be polled.
2. The four-deep FIFO is not available in the transmit path.
3. The TXSPIx register is used to transmit data.
Master Mode DMA Operation
To configure the SPI port for master mode DMA transfers:
1. Specify which FLAG pins to use as the slave-select signals by setting
one or more of the
DSxEN bits (bits 3–0) in the SPI flag (SPIFLGx)
registers.
2. Enable the device as a master and configure the SPI system by
selecting the appropriate word length, transfer format, baud rate,
and so on in the SPIBAUDx and SPICTLx registers. The TIMOD field
(bits 1–0) in the
SPICTLx registers is configured to select transmit
or receive with DMA mode (
TIMOD = 10).
3. Activate the desired slaves by clearing one or more of the SPI flag
bits (
SPIFLGx) of SPIFLGx registers if CPHASE = 1.
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