SPI Data Transfer Operations
6-24 ADSP-21368 SHARC Processor Hardware Reference
3. Clear all errors by writing to the W1C-type bits in the
SPISTATx
registers. This ensures that no interrupts occur due to errors from a
previous DMA operation.
4. Reconfigure the SPICTL register to remove the clear condition on
the TXSPI/RXSPI registers.
5. Configure DMA by writing to the DMA parameter registers and
enable DMA.
Switching From Receive to Transmit DMA
Use the following sequence to switch from receive to transmit DMA. Note
that TXSPIx and RXSPIx are registers but they may not contain any bits,
only address information.
With disabling of the SPI:
1. Write 0x00 to the SPICTLx registers to disable the SPI. Disabling
the SPI also clears the contents of the RXSPIx/TXSPIx registers and
the buffer status.
2. Disable DMA and clear the DMA FIFO by writing 0x80 to the
SPIDMACx registers. This ensures that any data from a previous
DMA operation is cleared because the SPICLK signal runs for five
more word transfers even after the DMA count falls to zero in the
receive DMA.
3. Clear all errors by writing to the SPISTATx registers. This ensures
that no interrupts occur due to errors from a previous DMA
operation.
4. Reconfigure the
SPICTLx registers and enable the SPI.
5. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx register.
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