ADSP-21368 SHARC Processor Hardware Reference 1-9
Introduction
ROM-Based Security. For those processors with application code in the
on-chip ROM, an optional ROM security feature is included. This feature
provides hardware support for securing user software code by preventing
unauthorized reading from the enabled code. The processor does not
boot-load any external code, executing exclusively from internal ROM.
Also, the processor is not freely accessible via the JTAG port. Instead, a
64-bit key is assigned to the user. This key must be scanned in through the
JTAG or Test Access Port. The device ignores a wrong key. Emulation
features and external boot modes are only available after the correct key is
scanned.
Digital Audio Interface (DAI)
The digital audio interface (DAI) unit is a new addition to the SHARC
processor peripherals. This set of audio peripherals consists of an interrupt
controller, an interface data port, and a signal routing unit, four precision
clock generators (PCGs) and three timers. Some family members have an
S/PDIF receiver/transmitter and eight channels asynchronous sample rate
converters (SRC).
Interrupt Controller. The DAI contains its own interrupt controller that
indicates to the core when DAI audio events have occurred. This interrupt
controller offer 32 independently configurable channels.
Input Data Port (IDP). The input data port provides the DAI with a way
to transmit data from within the DAI to the core. The IDP provides a
means for up to eight additional DMA paths from the DAI into on-chip
memory. All eight channels support 24-bit wide data and share a 16-deep
FIFO.
Signal Routing Unit One (SRU1). Conceptually similar to a “patch-bay”
or multiplexer, the SRU provides a group of registers that define the inter-
connection of the serial ports, the input data port, the DAI pins, and the
precision clock generators.
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