Architectural Overview
1-8 ADSP-21368 SHARC Processor Hardware Reference
same serial clock and frame sync. Accordingly, each serial port has two
DMA channels and serial data buffers associated with it to service the dual
serial data pins. Programmable data direction provides greater flexibility
for serial communications. Serial port data can automatically transfer to
and from on-chip memory using DMA. Each of the serial ports offers a
TDM multichannel mode (up to 128 channels) and supports μ-law or
A-law companding. I
2
S support is also provided with the
ADSP-21367/8/9 and ADSP-2137x processors.
The serial ports can operate with least significant bit first (LSBF) or most
significant bit first (MSBF) transmission order, with word lengths from 3
to 32 bits. The serial ports offer selectable synchronization and transmit
modes. Serial port clocks and frame syncs can be internally or externally
generated.
Serial Peripheral (Compatible) Interface (SPI). The SPI is an industry
standard synchronous serial link that enables the SPI-compatible port to
communicate with other SPI-compatible devices. SPI is an interface con-
sisting of two data pins, one device select pin, and one clock pin. It is a
full-duplex synchronous serial interface, supporting both master and slave
modes. It can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a master or slave
device.
The SPI-compatible peripheral implementation also supports programma-
ble baud rate and clock phase/polarities, as well as the use of open drain
drivers to support the multimaster scenario to avoid data contention.
SDRAM Controller. The SDRAM controller provides an interface of up
to four separate banks of industry-standard SDRAM devices or DIMMs,
at speeds up to
f
SCLK
. Fully compliant with the SDRAM standard, each
bank has it’s own memory select line (
MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
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