ADSP-21368 SHARC Processor Hardware Reference 6-9
Serial Peripheral Interface Ports
SPI Enable
For slaves, the slave-select input acts like a reset for the internal SPI logic.
For this reason, the SPIDS line must be error free. The SPIEN signal can
also be used as a software reset of the internal SPI logic. An exception to
this is the W1C-type (write 1-to-clear) bits in the SPISTATx (SPI status)
registers which remain set if they are already set. For a list of write W1C
bits, see Table A-11 on page A-57.
L
Always clear the W1C-type bits before re-enabling the SPI, as these
bits do not get cleared even if SPI is disabled. This can be done by
writing 0xFF to the SPISTATx registers. In the case of an MME error,
enable the SPI ports after SPIDS is deasserted.
Open Drain Mode (OPD)
In a multimaster or multislave SPI system, the data output pins (MOSI and
MISO) can be configured to behave as open drain drivers to prevent possi-
ble damage to pin drivers due to contention. An external pull-up resistor is
required on both the MOSI and MISO pins when this option is selected.
When the OPD bit is set and the SPI ports are configured as masters, the
MOSI pin is three-stated when the data driven out on MOSI is logic high.
The MOSI pin is not three-stated when the driven data is logic low. A zero
is driven on the MOSI pin in this case. Similarly, when OPD is set and the
SPI ports are configured as slaves, the
MISO pin is three-stated if the data
driven out on MISO is logic high.
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