ADSP-21368 SHARC Processor Hardware Reference A-57
Register Reference
Table A-11. SPISTAT Register Bit Descriptions
Bit Name Description
0SPIF SPI Transmit or Receive Transfer Complete. SPIF is set when an
SPI single-word transfer is complete.
1 MME Multimaster Error or Mode-Fault Error. MME is set in a master
device when some other device tries to become the master.
2TUNFTra n s m i s s i o n E r r o r. TUNF is set when transmission occurred with
no new data in TXSPI register.
3TXS Transmit Data Buffer Status. TXSPI data buffer status.
0 = Empty
1 = Full
4ROVF Reception Error. ROVF is set when data is received with receive
buffer full
5RXS Receive Data Buffer Status.
0 = Empty
1 = Full
6TXCOLTransmit Collision Error. When TXCOL is set, it is possible that
corrupt data was transmitted.
7SPIFE External Transaction Complete. Set (= 1) when the SPI transaction
is complete on the external interface.
31-8 Reserved
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