Processor Pin Descriptions
14-8 ADSP-21368 SHARC Processor Hardware Reference
•
DATA9 pin is not used
• DATA8 pin acts as PDAP STROBE (output)
Interrupt and Timer Pins
The processor’s external interrupt pins, flag pins, and timer pin can be
used to send and receive control signals to and from other devices in the
system. The
IRQ2–0 pins are mapped on the FLAG2–0 pins and the TIMEXP
pin is mapped on the
FLAG3 pin. Hardware interrupt signals (IRQ2–0) are
received on the FLAG2–0 pins. Interrupts can come from devices that
require the processor to perform some task on demand. A
memory-mapped peripheral, for example, can use an interrupt to alert the
processor that it has data available. For more information, see
Appendix B, Interrupts..
The TIMEXP output is generated by the on-chip timer. It indicates to other
devices that the programmed time period has expired. For more informa-
tion, see the ADSP-2136x SHARC Processor Programming Reference.
Core-Based Flag Pins
The FLAG3–0 pins allow single bit signalling between the processor and
other devices. For example, the processor can raise an output flag to inter-
rupt a host processor. Each flag pin can be programmed to be either an
input or output. In addition, many processor instructions can be condi-
tioned on a flag’s input value, enabling efficient communication and
synchronization between multiple processors or other interfaces.
The flags are bidirectional pins and all have the same functionality. The
FLGxO bits in the FLAGS register program the direction of each flag pin. For
more information, see the ADSP-2136x SHARC Processor Programming
Reference.
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