ADSP-21368 SHARC Processor Hardware Reference 11-13
UART Port Controller
For information on UART DMA registers, see “UART DMA” on
page 2-44.
UARTxMODE Register
The UART mode register controls miscellaneous settings such as packing
and address detection. For more information, see “Mode Registers (UAR-
TxMODE)” on page A-126.
I/O Mode
In I/O mode, data is moved to and from the UART by the processor core.
To transmit a character, load it into the UARTxTHR register. Received data
can be read from the UARTxRBR register. The processor must write and read
one character at time.
To prevent any loss of data and misalignments of the serial data stream,
the UART line status register (UARTxLSR) provides two status flags for
handshaking—UARTTHRE and UARTDR.
The UARTTHRE flag is set when the UARTxTHR register is ready for new data
and cleared when the processor loads new data into the UARTxTHR register.
Writing this register when it is not empty overwrites the register with the
new value and the previous character is never transmitted.
The
UARTDR flag signals when new data is available in the UARTxRBR regis-
ter. This flag is cleared automatically when the processor reads from this
register. Reading the UARTxRBR register when it is not full returns the pre-
viously received value. When the
UARTxRBR register is not read in time,
newly received data overwrites the
UARTxRBR register and the overrun (UAR-
TOE
) flag is set.
With interrupts disabled, these status flags can be polled to determine
when data is ready to move. Note that because polling is processor-inten-
sive, it is not typically used in real-time signal processing environments.
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