ADSP-21368 SHARC Processor Hardware Reference 2-35
I/O Processor
All of the I/O processor’s registers are memory-mapped, ranging from
address 0x0000 0000 to 0x0003 FFFF. For more information on these
registers, see “I/O Processor Registers” on page A-2.
External Port DMA
The external port has two DMA channels that can use either the SDRAM
controller (SDC) or the asynchronous memory interface (AMI). The
DMA chooses the correct interface (AMI or SDC) based on the external
address as determined by bits 0–3 in the external port global control regis-
ter (
EPCTL, Table A-3 on page A-11). The DMA controllers support
conventional DMA, chained and circular DMA, and delay line DMA. The
priority of the two DMA channels is fixed with external port 0 having pri-
ority over external port 1.
The DMA controllers have two FIFOs, a four deep data FIFO for
received/transmitted data and a four deep tap list FIFO for the tap list
entries for the delay line DMA.
The registers that control external port DMA are described in Table 2-8.
32 TXCTL_UAC0 TXI_UAC0, TXM_UAC0,
TXC_UAC0, TXCP_UAC0,
TXSTAT_UAC0
THR0 UART0 Tx
33 TXCTL_UAC1 TXI_UAC1, TXM_UAC1,
TXC_UAC1, TXCP_UAC1,
TXSTAT_UAC1
THR1 UART1 Tx
Table 2-7. DMA Channel Registers: Controls, Parameters,
and Buffers (Cont’d)
DMA
Channel
Number
Control Registers Parameter Registers Buffer Registers Description
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