FIFO to Memory Data Transfer
7-20 ADSP-21368 SHARC Processor Hardware Reference
• When the data transfer to the core is 32 bits, as in the case of
PDAP data or I
2
S and left-justified modes with 32 bits, there is no
channel information in the data. Therefore, PDAP or I
2
S and
left-justified 32 bit modes can not be used with other channels in
the core/interrupt-driven mode.
IDP Transfers Using DMA
The ADSP-21367/8/9 and ADSP-2137x processors support two types of
DMA transfers, simple and ping-pong.
Simple DMA
This DMA access is enabled when the IDP_DMA_EN bit (bit 5 of the
IDP_CTL0 register) is set (= 1) and the IDP_DMA_ENx bits in the IDP_CTLl
register are set to select a particular channel.
The DMA is performed according to the parameters set in the various
DMA registers and IDP control registers. The DMA transfer is completed
when the count register (IDP_DMA_Cx) reaches zero. The IDP_DMA_EN bit
and IDP_DMA_ENx bits must be reset before starting another DMA. An
interrupt is generated at the end of DMA transfer.
Starting a Simple DMA Transfer
To start a DMA transfer from the FIFO to memory:
1. Clear and halt the FIFO by setting (= 1) and then clearing (= 0) the
IDP_ENABLE bit (bit 7 in the IDP_CTL0 register).
2. While the IDP_DMA_EN and IDP_ENABLE bits are low, set the values
for the DMA parameter registers that correspond to channels 7–0.
If some channels are not going to be used, then the corresponding
parameter registers can be left in their default states:
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