ADSP-21368 SHARC Processor Hardware Reference 7-21
Input Data Port
• Index registers (
IDP_DMA_Ix)
• Modifier registers (IDP_DMA_Mx)
• Counter registers (IDP_DMA_Cx)
For each of these registers, x is 0 to 7. Refer to “DMA
Channel Parameter Registers” on page 7-27.
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the
SRU_CLK2, SRU_CLK3, SRU_FS2, and SRU_FS3 registers.
4. Set required values for:
• IDP_SMODEx bits in the IDP_CTL0 register to specify the frame
sync format for the serial inputs (left-justified sample pair,
right-justified sample pair, or I
2
S modes).
• IDP_Pxx_PDAPMASK bits in the IDP_PP_CTL register to specify
the input mask, if the PDAP is used.
• IDP_PORT_SELECT bits in the IDP_PP_CTL register to specify
input from the DAI pins or the IDP, if the PDAP is used.
• IDP_PDAP_CLKEDGE bit (bit 29) in the IDP_PP_CTL register to
specify if data is latched on the rising or falling clock edge, if
the PDAP is used.
5. Connect all of the inputs to the IDP by writing to the SRU_DAT4,
SRU_DAT5, SRU_FS2, SRU_FS3, SRU_CLK2, and SRU_CLK3 registers.
Keep the clock and frame sync of the ports connected to low when
data transfer is not intended.
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