ADSP-21368 SHARC Processor Hardware Reference 5-9
Serial Ports
A channel, the data is (optionally) expanded (SPORT1, 3, and 5 only),
then automatically transferred to the
RXSPxA buffer. When an entire word
is shifted in on the secondary channel, it is automatically transferred to the
RXSPxB buffer.
When the SPORT is configured as a receiver (SPTRAN = 0), the RXSPxA and
RXSPxB buffers are activated along with the corresponding A and B chan-
nel receive shift registers, responding to SPORTx_CLK and SPORTx_FS for
reception of data. The transmit TXSPxA and TXSPxB buffer registers and
transmit A and B shift registers are inactive and do not respond to the
SPORTx_CLK and SPORTx_FS. Since the TXSPxA and TXSPxB buffers are inac-
tive, writing to a transmit data buffer causes the core to hang indefinitely.
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If the SPORTs are configured as receivers (SPTRAN bit = 0 in
SPCTLx), programs should not write to the inactive TXSPxA and
TXSPxB buffers. If the core keeps writing to the inactive buffer, the
transmit buffer status becomes full. This causes the core to hang
indefinitely since data is never transmitted out of the deactivated
transmit data buffers.
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The processor’s SPORTs are not UARTs and cannot communicate
with an RS-232 device or any other asynchronous communications
protocol. Instead, the ADSP-21367/8/9 and ADSP-2137x proces-
sors have two dedicated UART peripherals. For more information,
see Chapter 11, UART Port Controller.
Serial Port Signal Sensitivity
There is some sensitivity to noise on the SPORTx_CLK and SPORTx_FS sig-
nals. In certain cases, by correctly programming the signal routing unit
(SRU1) clock and frame sync registers, the reflection sensitivity in these
signals can be avoided.
Consider this SPORT clock example. In its default routing, SRU1 maps
the signal from the DAI pin (
DAI_PBxx_O) back to the sport clock input
(
SPORTx_CLK_I), as well as routing the SPORT clock output
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