Frame Sync Options
5-38 ADSP-21368 SHARC Processor Hardware Reference
Internal Versus External Frame Syncs
Both transmit and receive frame syncs can be generated internally or input
from an external source. The IFS bit of the SPCTLx control registers deter-
mines the frame sync source.
When IFS is set (=1), the corresponding frame sync signal is generated
internally by the processor, and the SPORTx_FS signal is an output. The
frequency of the frame sync signal is determined by the value of the frame
sync divisor (
FSDIV) in the DIVx registers. Refer to Figure 5-10 on
page 5-70.
When IFS is cleared (=0), the corresponding frame sync signal is accepted
as an input on the SPORTx_FS signals, and the frame sync divisors in the
DIVx registers are ignored.
All frame sync options are available whether the signal is generated inter-
nally or externally.
Figure 5-7. Framed Versus Unframed Data
SPORTX_CLK
FRAMED
DATA
UNFRAMED
DATA
B3
B2 B1 B0 B3
B2 B1 B0
B3
B2 B1 B0 B3
B2 B1 B0
B3
B2 B1
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