SPI Data Transfer Operations
6-14 ADSP-21368 SHARC Processor Hardware Reference
• When a master is configured with
TIMOD = 00 and the receive buffer
becomes full the SPI device stalls the SPI clock until all of the data
is read from the receive buffer.
SPI Operation Using DMA
Each SPI has a single DMA channel associated with it that can be config-
ured to support either an SPI transmit or a receive, but not both
simultaneously. In addition to the TXSPIx and RXSPIx data buffers, there is
a four-word deep DMA FIFO that the SPI ports use to improve the data
throughput.
The SPI ports support both master and slave mode DMA. The following
sections describe master and slave mode DMA operations, DMA chaining,
switching between transmit and receive DMA operations, and processing
DMA interrupt errors. The following are guidelines to follow when per-
forming DMA transfers over the SPI.
• Do not write to the TXSPIx registers during an active SPI transmit
DMA operation because DMA data will be overwritten.
• Similarly, do not read from the RXSPIx registers during active SPI
DMA receive operations because DMA data will be overwritten.
• Writes to the TXSPIx registers during an active SPI receive DMA
operation are permitted. The
RXS register is cleared when the
RXSPIx registers are read.
• Reads from the RXSPIx registers are allowed at any time during
transmit DMA.
• Interrupts are generated based on DMA events and are configured
in the SPIDMACx registers.
In order for a transmit DMA operation to begin, the transmit buffer must
initially be empty (TXS = 0). While this is normally the case, this means
that the
TXSPIx registers should not be used for any purpose other than
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