ADSP-21368 SHARC Processor Hardware Reference 7-1
7 INPUT DATA PORT
The signal routing unit (SRU) provides paths among both on-chip and
off-chip peripherals. To make this feature effective in a real-world system,
a low overhead method of making data from various serial and parallel for-
mats and routing them back to the main core memory is needed. The
input data port (IDP) provides this mechanism for a large number of
asynchronous channels.
This chapter describes how data is routed into the core’s memory space.
Figure 7-1 provides a graphical overview of the input data port architec-
ture. Notice that each channel is independent and each contains a separate
clock and frame sync input.
Channels 0 through 7 can accept serial data in audio format. Channel 0
can also be configured to accept parallel data. The parallel input bypasses
the serial-to-parallel converter and latches up to 20 bits per clock cycle.
The parallel data is acquired through the parallel data acquisition port
(PDAP) which provides a means of moving high bandwidth data to the
core’s memory space. The data may be sent to memory as one 32-bit word
per input clock cycle or packed together (for up to four clock cycles worth
of data). Figure 7-2 on page 7-3 illustrates the data flow for IDP channel
0, where either the PDAP or serial input can be selected via
IDP_PDAP_EN
(bit 31 of the IDP_PP_CTL register). At the falling edge of IDP_PDAP_EN, the
FIFO is cleared. Data transfer from the channels to the FIFO happens on
a fixed priority with channel 0 having the highest priority and channel 7
the lowest.
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